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 Session Numbers
1A Machine Learning in VLSI Design, Yield Estimation and Post-Silicon Validation
1B Optimization Techniques for Upcoming Embedded Systems
1C Self-aware Systems-on-Chip
1D Formal Methods for Emerging Technologies
2A High-Level and Sequential Synthesis
2B Keep Austin Wired: Routing and Clocking
2C Hardware Based Authentication
2D Dennard Scaling is History and Moore's Law is Aging: How to Break the Inevitable Power Wall?
3A Design Automation for Non-Traditional Architectures
3B Modeling, Optimization, and Synthesis of Cyberphysical Systems
3C The Art of Engineering Heterogeneous Computing Systems
3D From EDA to DA: Can We Evolve Beyond Our E-Roots?
4A Reliability Goes Vertical
4B Advancements in Adaptive Test, 3D-IC Yield Improvement, and Silicon Debug
4C Accelerators for High Performance Data Analytics
4D Hardware Authentication: From ICs to IoTs
5A Simulation for Parallel and Accelerated Computing
5B This Is How We Shrink
5C State-Less Synthesis
5D The Landscape of Smart Buildings: Modeling, Management and Infrastructure
6A New CAD Directions for Emerging Technologies
6B Modern-Day Placement
6C Hardware Security: Methods and Metrics
6D Variability, Noise, and Nonlinearity
7A Embedded Software and Compilation Techniques for Power Efficiency
7B Design and Optimization of Cyberphysical Energy Systems
7C Synthesis and Methodology for Analog and Interconnect
7D Smart Chip for Smart Learning
8A A New Perspective on MPSoC: From Memories to NoCs
8B Emerging Directions for Timing and Power Delivery Network Analysis
8C Remodel, Redesign, and Reconfigure for Reliability
8D Design for Big Data: From Architecture to Service - An Industrial Perspective
9A Make or Break - Synthesis, Simulation and Post-Silicon Validation
9B Reducing Power and Lowering Temperature, Approximately!
9C Physical Optimization
9D System Level Design Challenges and Solutions: From Memory to the Cloud
10A TAU 2015 Contest on Incremental Timing and CPPR Analysis
10B 2015 CAD Contest
10D Rebooting Computing and Low­ Power Image Recognition Challenge
50 Workshop 1: Hardware and Algorithms for Learning On-a-Chip (HALO)
51 Workshop 2: Ninth International Workshop on Constraints in Formal Verification (CFV'15)
52 Workshop 3: Workshop on Efficient Computing in the Dark Silicon Era
53 Workshop 4: Frontiers in Analog CAD
54 Workshop 5: 8th IEEE/ACM Workshop on Variability Modeling and Characterization
55 Workshop 4: Frontiers in Analog CAD