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 Session Numbers
1A Emerging Memory Technologies
1B Novel Techniques for Manufacturability and Layout Migration
1C Making Timing Variations Irrelevant
1D Advances in Modeling and Optimization: From System Level to Mixed Signal Designs
2A Performance Evaluation of Multicore Systems: From Traffic Analysis to Latency Predictions
2B Improving Test Quality, Manufacturability & Reliability
2C CAD Approaches for Emerging Applications
2D From Application to Emerging Devices: Analog is Between a Rock and a Hard Place
3A Keeping Kilo-Core Chips Cool: New Directions and Emerging Solutions
3B Triple Patterning, Triple the Trouble?
3C Emerging Design Automation: The Movement to Apply CAD Techniques to Global Challenges
3D Emerging Directions in Hardware Synthesis
4A Thermal Management
4B 2013 CAD Contest
4C Modelling of Through Silicon Vias Parasitics and Shallow Trench Isolation Stress Effects
4D System-Level and Post-Silicon Validation
5A Power Considerations in System Design
5B Placement
5C Lifetime Analysis of TSV-Based 3D ICs
5D Test and Security for Analog and Mixed-Signal Circuits
6A To Remember or Not: Embedded Memories
6B Power, Timing and Noise Analysis and Optimization
6C Intelligent Compilation for Emulation and Acceleration
6D Analog and RF
7A Efficient and Secure Embedded Processors
7B Novel EM-IR for Power Grids
7C FPGA-Based Application Acceleration: Case Study with GZIP Compression/Decompression Streaming Engine
7D FinFET: A Multifaceted Perspective for CAD Engineers
8A Beyond Charge-Based Computing
8B Verification of Large Scale Designs
8C Tree Optimization in Physical Synthesis
8D New Frontiers in EDA for Neural and Microfluidic Circuits
9A Customized and Heterogeneous Architectures
9B Formal and Symbolic Verification
9C Clock Synthesis, ECO, and PCB Routing
9D Just Like How We Designed VLSI Circuit and System: Design Automation is Also Essential to System Biology
10A Emerging System Level Design
10B Advances in Logic Synthesis
10C Stochastic Circuit Simulation
10D Trustworthy Hardware
20 Workshop 1: International Workshop on Design Automation for Analog and Mixed-Signal Circuits
21 Workshop 2: IEEE/ACM Workshop on Variability Modeling and Characterization (VMC) 2013
22 Workshop 3: Eighth International Workshop on Constraints in Formal Verification (CFV), 2013
30 The Future of Computing through Brain-Inspired Architectures
31 Networks of NMOS and Neurons